This invention relates to integrated semiconductor devices and methods of manufacture, and more particularly to an improved method of making complementary insulated gate field effect (CMOS) transistors in integrated circuit form.
Complementary FET or "CMOS" devices have long been recognized as offering significant advantages in the area of low power consumption. However, most MOS memory and processor type devices now being manufactured are N-channel because of speed, circuit density and cost factors which heretofore have favored NMOS over CMOS. A process which reverses the usual sequence of making CMOS devices is disclosed in copending application Ser. No. 081,513, filed Oct. 3, 1979, assigned to Texas Instruments; the P-channel transistors are formed in N-type tanks in a P-type substrate so the method resembles the standard N-channel silicon gate process. Prior CMOS methods had formed N-channel transistors in P-type tanks in an N-type substrate.
As an improvement in the reversed CMOS process, it has been found that significant advantages result in a method which employs self-aligning implants adjacent each gate in the source-drain areas as will be explained.
It is the principal object of this invention to provide improved CMOS integrated circuit devices and an improved method of making such devices. Another object is to provide CMOS devices and methods of making devices which allow the speed advantage of N-channel transistors to be utilized, and which provide smaller size or higher circuit density with higher speed and/or lower cost. A further object is to provide CMOS devices which have self-aligned gates and yet allow polysilicon to cross over moat regions without forming transistors.